this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 / jan .9 9 hyundai semiconductor hy628400 a series 512kx8bit cmos sram description the hy628400 a is a high-speed, low power and 4m bits cmos sram organized as 524,288 words by 8 bits. the hy628400 a uses hyundai's high performance twin tub cmos process technology and was designed for high-speed and low power circuit technology. it is particularly well suited for use in high-density and low power system applications. this device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0v. features fully static operation and tri-state outputs ttl compatible inputs and outputs low power consumption battery backup(l/ll-part) - 2.0v(min) data retention standard pin configuration - 32pin 525mil sop - 32pin 400mil tsop-ii (standard and reversed) product voltage speed operation standby current( ua) temperature no. (v) ( ns) current( ma) l ll ( c ) hy628400 a 5.0 55/70/85 10 100 30 0~70(normal) note 1. normal : normal temperature 2. current value are max. pin connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a17 a17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss sop tsop-ii(standard) tsop-ii(reversed) pin description block diagram pin name pin function /cs chip select /we write enable /oe output enable a0 ~ a18 address input i/o1 ~ i/o8 data input/output vcc power(5.0v) vss ground a18 column decoder a0 row decoder memory array 1024x4096 sense amp output buffer i/o1 i/o8 add input buffer /cs /oe /we write driver control logic
hy628400 a series rev.0/ jan99 2 ordering information part no. speed power temp package hy628400 a lg 55/70/85 l-part sop hy628400 a llg 55/70/85 ll-part sop hy628400 a lt2 55/70/85 l-part tsop-ii(standard) hy628400 a llt2 55/70/85 ll-part tsop-ii(standard) hy628400 a lr2 55/70/85 l-part tsop-ii(reversed) hy628400 a llr2 55/70/85 ll-part tsop-ii(reversed) absolute maximum rating (1) symbol parameter rating unit remark vcc, v in, v out power supply, input/output voltage -0.5 to 7.0 v t a operating temperature 0 to 70 c hy628400 a t stg storage temperature -65 to 125 c p d power dissipation 1.0 w t solder lead soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliablity. recommended dc operating condition t a =0 ? to 70 ? (normal) symbol parameter min. typ. max. unit vcc supply voltage 4.5 5.0 5.5 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0.5 v v il input low voltage -0.5 (1) - 0.8 v note : 1. v il = -3.0v for pulse width less than 30ns truth table /cs1 /we /oe mode i/o operation h x x standby high-z l h h output disabled high-z l h l read data out l l x write data in note : 1. h=v ih , l=v il , x=don't care
hy628400 a series rev.0/ jan99 3 dc electrical characteristics vcc = 5.0v 10%, t a = 0 c to 70 c (normal) unless otherwise specified symbol parameter test condition min . typ . max . unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or or / oe = v ih or /we = v il -1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il, i i/o = 0ma - 5 10 ma i cc1 average operating current /cs = v il min duty cycle = 100%, i i/o = 0ma - 50 80 ma i sb ttl standby current (ttl input) /cs = v ih - 0.4 2 ma i sb1 standby current hy628400 a /cs > vcc - 0.2v l - - 100 ua (cmos input) ll - - 30 ua v ol output low voltage i ol = 2.1ma - - 0.4 v v oh output high voltage i oh = -1ma 2.4 - - v note : typical values are at vcc = 5.0v, t a = 25 c ac characteristics vcc = 5.0v 10%, t a = 0 c to 70 c (normal) unless otherwise specified -55 -70 -85 min. max. min. max. min max. 1 trc read cycle time 55 - 70 - 85 - ns 2 taa address access time - 55 - 70 - 85 ns 3 tacs chip select access time - 55 - 70 - 85 ns 4 toe output enable to output valid - 25 - 35 - 45 ns 5 tclz chip select to output in low z 10 - 10 - 10 - ns 6 tolz output enable to output in low z 5 - 5 - 5 - ns 7 tchz chip deselecting to output in high z 0 20 0 25 0 30 ns 8 tohz out disable to output in high z 0 20 0 25 0 30 ns 9 toh output hold from address change 10 - 10 - 10 - ns 10 twc write cycle time 55 - 70 - 85 - ns 11 tcw chip selection to end of write 45 - 60 - 70 - ns 12 taw address valid to end of write 45 - 60 - 70 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width 40 - 50 - 55 - ns 15 twr write recovery time 0 - 0 - 0 - ns 16 twhz write to output in high z 0 20 0 25 0 30 ns 17 tdw data to write time overlap 25 - 30 - 35 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 5 - 5 - 5 - ns read cycle write cycle symbol parameter # unit
hy628400 a series rev.0/ jan99 4 ac test conditions t a = 0 c to 70 c (normal ) unless otherwise specified parameter value input pulse level 0.8v to 2.4v input rise and fall time 5ns input and output timing reference level 1.5v output load cl = 100pf + 1ttl load ac test loads cl(1) ttl note : including jig and scope capacitance capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf note : this parameter is sampled and not 100% tested
hy628400 a series rev.0/ jan99 5 timing diagram read cycle 1 addr oe cs data out data valid trc tacs tclz toe tolz taa toh tohz tchz high-z note(read cycle): 1. tchz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. at any given temperature and voltage condition, tchz max. is less than tclz min. both for a given device and from device to device. 3. /we is high for the read cycle. read cycle 2 trc taa data valid previous data toh toh addr data out note(read cycle): 1. /we is high for the read cycle. 2. device is continuously selected /cs = v il 3. /oe =v il .
hy628400 a series rev.0/ jan99 6 write cycle 1(/oe clocked) addr oe cs data out twc tdw tohz we data valid tdh twp tas data in twr tcw taw write cycle 2 (/oe low fixed) tdw twhz we data valid tdh twp tas data in twr tcw taw (7) (8) tow addr cs data out twc notes(write cycle): 1. a write occurs during the overlap of a low /cs and low /we. a write begins at the latest transition among /cs going low /we going low: a write end at the earliest transition among /cs going high and /we going high. twp is measured from the beginning of write to the end of write. . 2. tcw is measured from the later of /cs going low to the end of write . 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. 5. if /oe and /we are in the read mode during this period, and the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 6. if /cs goes low simultaneously with /we going low, the outputs remain in high impedance state. 7. dout is the read data of the new address. 8. when /cs is low, i/o pins are in the output state. the input signals in the opposite phase leading to the outputs should not be applied.
hy628400 a series rev.0/ jan99 7 data retention electric charateristic t a =0 c to 70 c (normal) symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v 2.0 - - v vss < v in < vcc i ccdr data retention hy628400 a vcc = 3.0v, l - - 50 ua current /cs > vcc - 0.2v ll - - 15 ua vss < v in < vcc tcdr chip deselect to data retention time 0 - - ns tr operating recovery time trc(2) - - ns notes: 1. typical values are at the comdition of t a = 25 c . 2. trc is read cycle time. data retention timing diagram cs vdr cs>vcc-0.2v tcdr tr vss vcc 4.5v 2.2v data retention mode reliability spec . test mode test spec. esd hbm > 2000v mm > 250v latch - up < -100 ma > 100 ma
hy628400 a series rev.0/ jan99 8 package information 32pin 400mil thin small outline package standard(t2) 0.404(10.2620) 0.396(10.0580() 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min. 32pin 400mil thin small outline package reversed(r2) 0.404(10.2620) 0.396(10.0580) 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050 bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min.
hy628400 a series rev.0/ jan99 9 32pin 525mil small outline package(g) unit : inch(mm) 0.444(11.27 8 ) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.810(20.574) 0.804(20.42 2 ) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.10 2 ) 0.020(0.508) 0.014(0.356) 0.050(1.27)bsc 0.0125(0.318) 0.0061(0.155) 0.0425(1.0 80 ) 0.0235(0.59 7 ) 0 deg 8 deg
|
